Spartan 6 Series Device

Spartan 6 Series Device Introduction

Overview of Spartan 6 devices

The Spartan 6 FPGA is a class of low-cost, high-capacity FPGAs that utilize 45nm low-power copper-laying technology to provide a good balance between power, performance, and cost; The Spartan6 family features a dual-register, 6-input LUT, and a series of built-in system-level modules, which include 18Kb Block Ram, a second-generation DSP48A21 Slice, an SDRAM memory interface (DDR interface), a robust Hybrid Clock Management Module, Select IO technology, an optimized High Speed Serial Transceiver GTP Transceiver, PCIE interface, advanced system-level power management modes, auto-detectable configurations, enhanced IP with AES and Device DNA protection. the Spartan6 is particularly well suited for high-volume logic designs, user-oriented DSP designs, and low-cost designs. If you want to learn more FPGA series, you can look at these FPGA series such as Zynq-7000 SoC, FPGA Spartan-7, Artix-7 FPGA, Virtex-7 FPGAs, Kintex-7 FPGAs, Virtex-6 FPGA, Spartan 6 FPGAs, and so on.

HTML Image as link
Spartan 6 Series Device

Figure 1: Spartan 6 FPGA device

Spartan 6 devices Features

  • Low design cost
  • Low dynamic and static power consumption

45nm technology optimized for power consumption

Zero power consumption in sleep mode

HTML Image as link

Suspend mode maintains the internal state of the chip and has multiple pins to enable wake-up of the chip

LX FPGAs, -1L uses 1.0V core voltage; LX and LXT FPGAs, -2, -3, and -3N use 1.2V core voltage

  • Select IO is available in multi-level standard

Up to 1080Mb/s data transfer rate per differential IO pair

Up to 24mA output current per pin

1.2–3.3V level standards and protocols for selection

Low-power HSTL, SSTL memory interface technology

Compliant with hot-swap specifications

Adjustable IO interface slice slopes for improved signal integrity

  • Endpoint block for PCIE interface design (only for LXT FPGA)
  • Supports PCI interface, compatible with 33MHZ, 32bit/64bit PCI protocol.
  • Highly efficient DSP48A1 module
  • High-speed serial transceiver (only for LXT FPGA)
  • Integrated memory control interface module

Supports DDR, DDR2, DDR3, and LPDDR

Data rates up to 800Mb/s

Memory control interface with multiple ports, each containing its own independent FIFO, enabling high-speed memory reads and writes

  • Sufficient logical resources

Optional shift register or distributed RAM

Efficient 6-input LUT

  • Simplified device configuration

Two pins for auto-detection of configuration mode

Supports SPI Flash (up to 4) and Nor Flash configurations

Xilinx Platform Flash programmed with JTAG 

Multi-boot support for easy remote upgrades

  • Security protection for designs
  • Unique Device DNA logo for design authentication
  • AES bitstream encryption
  • Support for MicroBlaze soft processor systems
  • Extensive industrial IP and reference designs

Applications of Spartan 6 FPGA

Industry-leading connection characteristics offered by SpartanTM 6 devices include high logic-to-pin ratios, tiny form factors, MicroBlazeTM soft processors, and a wide range of supported I/O protocols. ideal for a variety of cutting-edge bridging uses in consumer electronics, automobile infotainment, and industrial automation. Spartan 6 FPGAs can be applied to Industrial Networks, Vehicle Networking and Connectivity, and High Resolution Video and Graphics.

Resources of Spartan6 FPGA

The following table shows the logical resources for each model of the Spartan-6 series, which is explained as follows:

Each SLICE contains 4 LUTs and 8 flip-flops.

Each DSP48A1 slice contains 1 18X18 multiplier, 1 48bit accumulator, 1 adder.

Each 18Kb Block RAM can be used as two 9Kb Block RAMs.

Each CMT contains 2 DCMs and 1 PLL.

No memory interface (DDR interface) in the -3N speed grade devices.
Spartan-6 FPGA Logic Resources

Figure 2: Spartan-6 FPGA Logic Resources

Spartan-6 Series IO Resources

Figure 3: Spartan-6 Series IO Resources

Overview of Spartan-6 Series Package 

The Spartan-6 family features a low-cost, space-saving package format that maximizes user pin density. Pin assignments are compatible between all Spartan-6 LX devices and between all Spartan-6 LXT devices, but not between Spartan-6 LX and Spartan-6 LXT devices.
Spartan-6 Series Package

Figure 4: Spartan-6 Series Package

Spartan-6 Series Pin Assignment

The Spartan-6 series has its own dedicated pins that are not available as Select IOs. These dedicated pins include: dedicated configuration pins, shown in Table 5. gtp high-speed serial transceiver pins, shown in Table 6.
Spartan-6 FPGA-specific configuration pins

Figure 5: Spartan-6 FPGA-specific configuration pins

Number of GTP channels in Spartan-6 devices

Figure 6: Number of GTP channels in Spartan-6 devices

The LX75T packages four GTP channels in the FG(G)484 and CS(G)484, while eight GTP channels are packaged in the FG(G)676; the LX100T packages four GTP channels in the FG(G)484 and CS(G)484, while eight GTP channels are packaged in the FG(G)676 and FG(G)900.

As shown in Table 7, the number of available IO pins varies for each model and package, for example, for the LX4 TQG144 device, it has a total of 144 pins, of which the number of IOs that can be used as single-ended IO pins is 102, which 102 single-ended pins can be used as 51 pairs of differential IOs, and the other 32 pins are for power supply or special functions such as configuration pins.Summary of IO resources available for each Spartan 6 series package model

Figure 7: Summary of IO resources available for each Spartan 6 series package model

Spread the love

Leave a Comment

Your email address will not be published. Required fields are marked *

Scroll to Top